1. Field of the Invention
The present invention relates to a logic synthesis method for generating logic circuit data from given functional-level logic data. More particularly, the invention relates to logic synthesis or incremental logic synthesis for generating, when an old logic before updating and an old circuit optimized to satisfy design requirements are present, a new circuit optimized to satisfy the design requirements based on a new logic partially changing from the old logic.
2. Description of the Related Art
In order to improve the efficiency of logic design of a digital system, logic design is generally performed by using a logic synthesis system which generates a logic circuit from given functional-level logic. It is essential that a logic synthesis system generates an optimized circuit satisfying design requirements, from given functional-level logic. Such an optimization function is provided in most of logic synthesis systems including commercially available systems. With these systems having an optimization function, the structure of a generated circuit becomes very different from the old circuit even if a change in the new logic is small.
An incremental logic synthesis method for generating a new circuit based on the new functional-level logic is described in the specification of U.S. Pat. No. 4,882,690, wherein when an old logic before updating and an old circuit generated from the old logic are present, a new circuit preserving design information of the portions which need not be modified is generated from a new logic partially different from the old logic.
FIG. 1 illustrates an operation environment, namely a logic synthesis process of a conventional incremental logic synthesis method. The left portion (200 to 213) of FIG. 1 shows the process flow of initial design. For the initial design, a system for capturing a functional-level logic representative of a function generates a functional-level file or old logic (step 200). A logic synthesis system generates a circuit file from the functional-level file or old logic (steps 210, 201 and 211). A layout system generates a circuit file with physical design information from the first circuit file (steps 202 and 212). If necessary, a circuit capture system generates a circuit file or old circuit with physical design information and manually optimized logic design information (steps 203 and 213).
The right portion (200 to 217) of FIG. 1 shows a process flow for logic change. For the logic change, the logic capture system updates the functional-level logic or old logic to generate an updated functional-level file or new logic (steps 200 and 214). The logic synthesis system generates an updated circuit file from the updated functional-level file or new logic (steps 201 and 215). A circuit updating system generates an updated circuit file with physical design information and manually optimized logic design information of the portions which need not be modified, from the updated circuit file and the circuit file with physical design information and manually optimized logic design information (steps 204, and 216). The circuit capture system manually provides physical design information of added or modified circuit portions, and if necessary, the circuit is further manually optimized to generate an updated circuit file or new circuit with physical design information and manually optimized logic design information (steps 203 and 207). The above-described incremental logic synthesis method assumes the use of a logic synthesis system inputted with a functional-level logic describing at least one flip-flop and at least one optimized Boolean equation, wherein the circuit updating system identifies the portions of the old circuit which need not be modified in accordance with the comparison of the structures between the old and new circuits.
If design requirements are very severe, the conventional logic synthesis system requires a very long optimization process time in order to satisfy the design requirements, resulting in a very long total time of logic synthesis. Therefore, with this logic synthesis system, the design time required for each logic change becomes long. Although an incremental logic synthesis method may be generally effective for solving this problem, the circuit updating system of the above-described conventional incremental logic synthesis method identifies the portions of the old circuit which need not be modified in accordance with the comparison of the structures between the old and new circuits. Therefore, if the generated circuit structure changes, identification of corresponding gate pairs through the structure comparison is hardly possible, so that optimization information of the old circuit can be hardly preserved.